A flip chip package includes a downward facing semiconductor chip electrically and mechanically attached to a substrate by solder bumps. Flip chip packages are usually preferred over other conventional packages because of the scalability of flip chip packages that allows their use in smaller applications. But as the sizes of flip chip packages decrease and as the uses of low-k dielectrics increase, problems with the bump pad metal and low-k dielectric may occur from mechanical stresses on the flip chip package.
FIG. 1A is a cross-sectional view of a solder bump pad and a portion of its underlying interconnect structure. A solder bump 2 is physically connected to an under bump metal (UBM) pad 4 that is connected to an aluminum pad 8 through an opening in an outer passivation layer 6 on a semiconductor chip. The aluminum pad 8 rests on an inner passivation layer 10. The inner passivation layer 10 is above an undoped silicon glass (USG) layer 12 that is on a low-k dielectric layer 14. The USG layer 12 may comprise multiple individual metal layers that comprise circuitry. An aluminum trace 16 electrically couples the aluminum pad 8 to an aluminum contact 18 in the interconnect structure. Vias 20a, 20b, and 20c through the inner passivation layer 10 connect the aluminum contact 18 to a contact 22. The contact 22 is coupled to another contact 26 through vias 24. Additional contacts and vias may comprise the interconnect structure as required by the semiconductor device.
FIG. 1B is a layout of the UBM pad 4, the aluminum pad 8, the aluminum trace 16, the aluminum contact 18, and vias 20a, 20b, and 20c. The outer octagonal area represents the aluminum pad 8. The middle octagonal area represents the UBM pad 4. The inner octagonal area represents the depressed portion of the UBM pad 4.
The bump pad illustrated in FIGS. 1A and 1B are generally used on flip chip assemblies. Flip chip assemblies are preferred in modern technologies because of their scalability for use in smaller technologies. Yet, as the assembly size decreases, particularly to 22 nm technology, and as low-k dielectric usage becomes more prevalent, particularly when the k value is less than 2.5, the impact of the mechanical stresses arising from the bump pad increases. Stresses on the bump pad, such as peeling or shear forces caused by coefficient of thermal expansion (CTE) mismatch between the semiconductor device and the attached package substrate, can cause mechanical failures of the semiconductor device, such as cracking of the USG, low-k dielectric, or solder bump, due to the weakened bump pad.
Another structure commonly used in flip chip technology is the direct bump on copper (DBOC) structure. In the DBOC structure, the UBM is in direct contact with the copper metal of the top metallization layer. No aluminum pad or inner passivation layer is used in the DBOC structure. Without an aluminum pad or an inner passivation layer to act as a buffer, a DBOC structure generally has less mechanical strength and suffers from the same problems as discussed above. Accordingly, there is a need in the prior art for a bump pad with increased mechanical strength to overcome the deficiencies of the prior art.